System and method for controlling central processing unit power with guaranteed transient deadlines

ABSTRACT

A method of controlling power at a central processing unit is disclosed. The method may include moving to a higher CPU frequency after a transient performance deadline has expired, entering an idle state, and resetting the transient performance deadline based on an effective transient budget.

RELATED APPLICATIONS

The present application claims priority to U.S. Provisional Patent Application Ser. No. 61/286,991, entitled SYSTEM AND METHOD OF DYNAMICALLY CONTROLLING POWER IN A CENTRAL PROCESSING UNIT, filed on Dec. 16, 2009, the contents of which are fully incorporated by reference.

CROSS-REFERENCED APPLICATIONS

The present application is related to, and incorporates by reference, U.S. patent application Ser. No. ______, entitled SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER BASED ON INFERRED WORKLOAD PARALLELISM, by Rychlik et al., filed concurrently (Attorney Docket Number 100328U1). The present application is related to, and incorporates by reference, U.S. patent application Ser. No. ______, entitled SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER IN A VIRTUALIZED SYSTEM, by Rychlik et al., filed concurrently (Attorney Docket Number 100329U1). The present application is related to, and incorporates by reference, U.S. patent application Ser. No. ______, entitled SYSTEM AND METHOD FOR ASYNCHRONOUSLY AND INDEPENDENTLY CONTROLLING CORE CLOCKS IN A MULTICORE CENTRAL PROCESSING UNIT, by Rychlik et al., filed concurrently (Attorney Docket Number 100330U1). The present application is related to, and incorporates by reference, U.S. patent application Ser. No. ______, entitled SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER WITH REDUCED FREQUENCY OSCILLATIONS, by Thomson et al., filed concurrently (Attorney Docket Number 100339U1). The present application is related to, and incorporates by reference, U.S. patent application Ser. No. ______, entitled SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER WITH GUARANTEED STEADY STATE DEADLINES, by Thomson et al., filed concurrently (Attorney Docket Number 100341U1). The present application is related to, and incorporates by reference, U.S. patent application Ser. No. ______, entitled SYSTEM AND METHOD FOR DYNAMICALLY CONTROLLING A PLURALITY OF CORES IN A MULTICORE CENTRAL PROCESSING UNIT BASED ON TEMPERATURE, by Sur et al., filed concurrently (Attorney Docket Number 100344U1).

DESCRIPTION OF THE RELATED ART

Portable computing devices (PDs) are ubiquitous. These devices may include cellular telephones, portable digital assistants (PDAs), portable game consoles, palmtop computers, and other portable electronic devices. In addition to the primary function of these devices, many include peripheral functions. For example, a cellular telephone may include the primary function of making cellular telephone calls and the peripheral functions of a still camera, a video camera, global positioning system (GPS) navigation, web browsing, sending and receiving emails, sending and receiving text messages, push-to-talk capabilities, etc. As the functionality of such a device increases, the computing or processing power required to support such functionality also increases. Further, as the computing power increases, there exists a greater need to effectively manage the processor, or processors, that provide the computing power.

Accordingly, what is needed is an improved method of controlling power within a multicore CPU.

BRIEF DESCRIPTION OF THE DRAWINGS

In the figures, like reference numerals refer to like parts throughout the various views unless otherwise indicated.

FIG. 1 is a front plan view of a first aspect of a portable computing device (PCD) in a closed position;

FIG. 2 is a front plan view of the first aspect of a PCD in an open position;

FIG. 3 is a block diagram of a second aspect of a PCD;

FIG. 4 is a block diagram of a processing system;

FIG. 5 is a flowchart illustrating a first aspect of a method of dynamically controlling power within a CPU;

FIG. 6 is a flowchart illustrating a first portion of a second aspect of a method of dynamically controlling power within a CPU;

FIG. 7 is a flowchart illustrating a second portion of the second aspect of a method of dynamically controlling power a multicore CPU;

FIG. 8 is an exemplary graph showing the dynamic clock and voltage scaling (DCVS) controlled CPU frequency plotted over time; and

FIG. 9 is an exemplary graph showing effective transient response times for various performance levels.

DETAILED DESCRIPTION

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

In this description, the term “application” may also include files having executable content, such as: object code, scripts, byte code, markup language files, and patches. In addition, an “application” referred to herein, may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.

The term “content” may also include files having executable content, such as: object code, scripts, byte code, markup language files, and patches. In addition, “content” referred to herein, may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.

As used in this description, the terms “component,” “database,” “module,” “system,” and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device may be a component. One or more components may reside within a process and/or thread of execution, and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components may execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems by way of the signal).

Referring initially to FIG. 1 and FIG. 2, an exemplary portable computing device (PCD) is shown and is generally designated 100. As shown, the PCD 100 may include a housing 102. The housing 102 may include an upper housing portion 104 and a lower housing portion 106. FIG. 1 shows that the upper housing portion 104 may include a display 108. In a particular aspect, the display 108 may be a touch screen display. The upper housing portion 104 may also include a trackball input device 110. Further, as shown in FIG. 1, the upper housing portion 104 may include a power on button 112 and a power off button 114. As shown in FIG. 1, the upper housing portion 104 of the PCD 100 may include a plurality of indicator lights 116 and a speaker 118. Each indicator light 116 may be a light emitting diode (LED).

In a particular aspect, as depicted in FIG. 2, the upper housing portion 104 is movable relative to the lower housing portion 106. Specifically, the upper housing portion 104 may be slidable relative to the lower housing portion 106. As shown in FIG. 2, the lower housing portion 106 may include a multi-button keyboard 120. In a particular aspect, the multi-button keyboard 120 may be a standard QWERTY keyboard. The multi-button keyboard 120 may be revealed when the upper housing portion 104 is moved relative to the lower housing portion 106. FIG. 2 further illustrates that the PCD 100 may include a reset button 122 on the lower housing portion 106.

Referring to FIG. 3, an exemplary, non-limiting aspect of a portable computing device (PCD) is shown and is generally designated 320. As shown, the PCD 320 includes an on-chip system 322 that includes a multicore CPU 324. The multicore CPU 324 may include a zeroth core 325, a first core 326, and an Nth core 327.

As illustrated in FIG. 3, a display controller 328 and a touch screen controller 330 are coupled to the multicore CPU 324. In turn, a touch screen display 332 external to the on-chip system 322 is coupled to the display controller 328 and the touch screen controller 330.

FIG. 3 further indicates that a video encoder 334, e.g., a phase alternating line (PAL) encoder, a sequential couleur a memoire (SECAM) encoder, or a national television system(s) committee (NTSC) encoder, is coupled to the multicore CPU 324. Further, a video amplifier 336 is coupled to the video encoder 334 and the touch screen display 332. Also, a video port 338 is coupled to the video amplifier 336. As depicted in FIG. 3, a universal serial bus (USB) controller 340 is coupled to the multicore CPU 324. Also, a USB port 342 is coupled to the USB controller 340. A memory 344 and a subscriber identity module (SIM) card 346 may also be coupled to the multicore CPU 324. Further, as shown in FIG. 3, a digital camera 348 may be coupled to the multicore CPU 324. In an exemplary aspect, the digital camera 348 is a charge-coupled device (CCD) camera or a complementary metal-oxide semiconductor (CMOS) camera.

As further illustrated in FIG. 3, a stereo audio CODEC 350 may be coupled to the multicore CPU 324. Moreover, an audio amplifier 352 may coupled to the stereo audio CODEC 350. In an exemplary aspect, a first stereo speaker 354 and a second stereo speaker 356 are coupled to the audio amplifier 352. FIG. 3 shows that a microphone amplifier 358 may be also coupled to the stereo audio CODEC 350. Additionally, a microphone 360 may be coupled to the microphone amplifier 358. In a particular aspect, a frequency modulation (FM) radio tuner 362 may be coupled to the stereo audio CODEC 350. Also, an FM antenna 364 is coupled to the FM radio tuner 362. Further, stereo headphones 366 may be coupled to the stereo audio CODEC 350.

FIG. 3 further indicates that a radio frequency (RF) transceiver 368 may be coupled to the multicore CPU 324. An RF switch 370 may be coupled to the RF transceiver 368 and an RF antenna 372. As shown in FIG. 3, a keypad 374 may be coupled to the multicore CPU 324. Also, a mono headset with a microphone 376 may be coupled to the multicore CPU 324. Further, a vibrator device 378 may be coupled to the multicore CPU 324. FIG. 3 also shows that a power supply 380 may be coupled to the on-chip system 322. In a particular aspect, the power supply 380 is a direct current (DC) power supply that provides power to the various components of the PCD 320 that require power. Further, in a particular aspect, the power supply is a rechargeable DC battery or a DC power supply that is derived from an alternating current (AC) to DC transformer that is connected to an AC power source.

FIG. 3 further indicates that the PCD 320 may also include a network card 388 that may be used to access a data network, e.g., a local area network, a personal area network, or any other network. The network card 388 may be a Bluetooth network card, a WiFi network card, a personal area network (PAN) card, a personal area network ultra-low-power technology (PeANUT) network card, or any other network card well known in the art. Further, the network card 388 may be incorporated into a chip, i.e., the network card 388 may be a full solution in a chip, and may not be a separate network card 388.

As depicted in FIG. 3, the touch screen display 332, the video port 338, the USB port 342, the camera 348, the first stereo speaker 354, the second stereo speaker 356, the microphone 360, the FM antenna 364, the stereo headphones 366, the RF switch 370, the RF antenna 372, the keypad 374, the mono headset 376, the vibrator 378, and the power supply 380 are external to the on-chip system 322.

In a particular aspect, one or more of the method steps described herein may be stored in the memory 344 as computer program instructions. These instructions may be executed by the multicore CPU 324 in order to perform the methods described herein. Further, the multicore CPU 324, the memory 344, or a combination thereof may serve as a means for executing one or more of the method steps described herein in order to a dynamically control the power of each CPU, or core, within the multicore CPU 324.

Referring to FIG. 4, a processing system is shown and is generally designated 500. In a particular aspect, the processing system 500 may be incorporated into the PCD 320 described above in conjunction with FIG. 3. As shown, the processing system 500 may include a multicore central processing unit (CPU) 402 and a memory 404 connected to the multicore CPU 402. The multicore CPU 402 may include a zeroth core 410, a first core 412, and an Nth core 414. The zeroth core 410 may include a zeroth dynamic clock and voltage scaling (DCVS) algorithm 416 executing thereon. The first core 412 may include a first DCVS algorithm 417 executing thereon. Further, the Nth core 414 may include an Nth DCVS algorithm 418 executing thereon. In a particular aspect, each DCVS algorithm 416, 417, 418 may be independently executed on a respective core 412, 414, 416.

Moreover, as illustrated, the memory 404 may include an operating system 420 stored thereon. The operating system 420 may include a scheduler 422 and the scheduler 422 may include a first run queue 424, a second run queue 426, and an Nth run queue 428. The memory 404 may also include a first application 430, a second application 432, and an Nth application 434 stored thereon.

In a particular aspect, the applications 430, 432, 434 may send one or more tasks 436 to the operating system 420 to be processed at the cores 410, 412, 414 within the multicore CPU 402. The tasks 436 may be processed, or executed, as single tasks, threads, or a combination thereof. Further, the scheduler 422 may schedule the tasks, threads, or a combination thereof for execution within the multicore CPU 402. Additionally, the scheduler 422 may place the tasks, threads, or a combination thereof in the run queues 424, 426, 428. The cores 410, 412, 414 may retrieve the tasks, threads, or a combination thereof from the run queues 424, 426, 428 as instructed, e.g., by the operating system 420 for processing, or execution, of those task and threads at the cores 410, 412, 414.

FIG. 4 also shows that the memory 404 may include a parallelism monitor 440 stored thereon. The parallelism monitor 440 may be connected to the operating system 420 and the multicore CPU 402. Specifically, the parallelism monitor 440 may be connected to the scheduler 422 within the operating system 420.

Referring to FIG. 5, a first aspect of a method of dynamically controlling the power of a central processing unit is shown and is generally designated 500. The method 500 may commence at block 502 with a do loop in which when device is powered on, the following steps may be performed.

At block 504, a power controller, e.g., a dynamic clock and voltage scaling (DCVS) algorithm, may monitor one or more CPUs. At decision 506, the power controller may determine whether a transient performance deadline for a CPU has expired. If not, the method 500 may end. Otherwise, if the transient performance deadline has expired, the method 500 may proceed to block 508 and the power controller may move the CPU to a higher performance level, i.e., a next higher operating frequency. In one aspect, the controller may move the CPU to a maximum performance level, i.e., a maximum CPU frequency. However, in another aspect, the CPU may not jump to a maximum performance level. The CPU may jump to an intermediate level and then, jump again, either to the maximum level or another higher performance level. The number of intermediate jumps may and the amount of time between jumps may be used to determine the frequency value of the jump.

At block 510, the CPU may enter an idle condition. Further, at block 512, the transient performance deadline may be reset. At block 514, the CPU may exit the idle condition. Moving to decision 516, the power controller may determine whether the upcoming CPU frequency is at a maximum CPU frequency. If so, the method 500 may end. Otherwise, if the CPU frequency is not at the maximum CPU frequency, the method may proceed to block 518 and the timer may be rescheduled. Then, the method 500 may end.

Referring to FIG. 6, a second aspect of a method of dynamically controlling the power of a central processing unit is shown and is generally designated 600. Beginning at block 602, a central processing unit (CPU) may enter an idle state. At block 604, a power controller, e.g., a dynamic clock and voltage scaling (DCVS) algorithm, may set a start idle time (StartIdleTime) equal to a current time (CurrentTime). Further, at block 606, the power controller may determine a busy time (BusyTime) by subtracting a start idle time (StartIdleTime) from an end idle time (EndIdleTime).

At block 608, the CPU may enter a software wait for interrupt (SWFI) condition. At block 610, the CPU may exit the SWFI condition. Moving to block 612, the power controller may set an end idle time (EndIdleTime) equal to a current time (CurrentTime). Further, at block 614, the power controller may determine an idle time (IdleTime) by subtracting the start idle time (StartIdleTime) from the end idle time (EndIdleTime). At block 616, the power controller may determine an upcoming CPU frequency (CPUFreq) from an updated steady state filter (UpdateSteadyStateFilter) a busy time (BusyTime) and an idle time (IdleTime). Thereafter, the method 600 may continue to block 702 of FIG. 7.

At block 702, the power controller may determine an effective transient budget (EffectiveTransientBudget) using the following formula:

EffectiveTransientBudget=(TransientResponseDeadline*NextCPUFreq)/(NextCPUFreq−CPUFreq)

where, TransientResponseDeadline=A transient response deadline, i.e., slack budget, NextCPUFreq=A next CPU frequency that is one frequency step higher than an upcoming CPU frequency, and CPUFreq=An upcoming CPU frequency (CPUFreq).

In a particular aspect, a clock scheduling overhead (ClockSchedulingOverhead) and a clock switch overhead (ClockSwitchOverhead) may also be added to the EffectiveTransientBudget. Further, a voltage change overhead (VoltageChangeOverhead) may be added to the EffectiveTransientBudget. Moving to block 704, the power controller may set a deadline to jump to a higher frequency (SetJumpToFrequency) equal to the end idle time (EndIdleTime) plus the effective transient budget (EffectiveTransientBudget). In another aspect, the deadline to jump may be the current time plus the transient budget. Thereafter, the method 600 may end.

In a particular aspect, the method 600 described in conjunction with FIG. 6 and FIG. 7 may be used to calculate the amount of time that the CPU may remain at the frequency determined by the DCVS before the transient deadline is exhausted and schedule a jump to the higher CPU frequency by that amount of time in the future. If idle is reentered prior to the jump to the higher frequency, the scheduled jump may be cancelled. The method 600 may delay the jump to the higher frequency by the amount of time determined as the EffectiveTransientBudget.

It is to be understood that the method steps described herein need not necessarily be performed in the order as described. Further, words such as “thereafter,” “then,” “next,” etc. are not intended to limit the order of the steps. These words are simply used to guide the reader through the description of the method steps. Moreover, the methods described herein are described as executable on a portable computing device (PCD). The PCD may be a mobile telephone device, a portable digital assistant device, a smartbook computing device, a netbook computing device, a laptop computing device, a desktop computing device, or a combination thereof.

In a particular aspect, a DCVS algorithm is a mechanism which measures CPU load/idle time and dynamically adjusts the CPU clock frequency to track the workload in an effort to reduce power consumption while still providing satisfactory system performance. As the workload changes, the change in CPU throughput may track, but also necessarily lag, the changes in the workload. Unfortunately, this may introduce a problem in cases where the workload has Quality of Service (QoS) requirements, as the DCVS algorithm may not track the workload quickly enough. Further, tasks may fail.

Many DCVS techniques involve measuring the steady state performance requirements of the CPU and setting the CPU frequency and voltage to the lowest level that may meet the steady state CPU usage. This is typically done by measuring the CPU utilization (percentage busy) over a period of time and setting the CPU performance level to one in which the average CPU utilization falls between a high and low threshold. The averaging period is optimized to minimize the frequency of changing clock frequencies, while maintaining reasonable responsiveness. In order to respond to transient workloads and/or the start of new workloads panic inputs may have been utilized to quickly bring up the CPU frequency.

In order to avoid the problem of the DCVS lagging the workload and causing tasks to fail, the system and methods disclosed herein provide a transient performance guarantee. The transient performance guarantee may be defined as the maximum amount of time that a continuously busy pulse may be delayed, as compared to running at the higher performance level. This may be accomplished by getting to the higher performance level prior to the transient performance deadline expiring and resetting the deadline whenever we go idle, since if the CPU is idle, it is by definition not in an oversubscribed state. As disclosed herein, the timer may be rescheduled to preserve the QoS guarantee whenever the system comes out of idle and the system CPU is not running at the maximum frequency.

In order to minimize the power impact of the transient performance guarantee, the present system and methods minimize the likely hood that an incoming pulse may require a frequency increase in order to meet the deadline. This may be accomplished by delaying the frequency, i.e., performance level, change until the effective transient budget has been exhausted and then, jumping straight to the higher performance level and staying there until the pulse is complete as shown in FIG. 8.

In a particular aspect, the effective transient budget is calculated as the transient response deadline scaled to the current performance level. For example, if the CPU is running a 75% of the maximum clock rate and the transient response deadline is 16 ms, the effective transient budget is 64 ms, i.e., 16 ms/(1-0.75). The effective transient budget represents how long the CPU may run at the current performance level prior to exhausting the budget. If the CPU is idle, the effective transient budget may be the same as the transient response deadline. If we are at the maximum performance level, the effective transient budget is infinite as shown in FIG. 9.

Using the methods described herein, the system may provide a strict bound on the maximum amount of time a task might run at some level other than the maximum level, and therefore implicitly provide a calculable bound on completion for tasks that require QoS guarantees, while still allowing dynamic CPU clock scaling. The bound may be set based on what tasks are currently running, a global system property, DCVS algorithm design or other properties, and may be entirely disabled if the system is not running any tasks that have QoS requirements or if the CPU is running at max clock.

In a particular aspect, the present methods may be extended by, instead of jumping to the maximum frequency when the deadline has expired, setting shorter internal effective deadlines and jumping to one, or more, intermediate frequencies, while still ensuring that the CPU is at the maximum frequency before the maximum QoS delay has been exhausted. Further, the present methods may substantially ensure that a well defined transient QoS is maintained, while simultaneously reducing overall CPU power.

The system and methods described herein may utilize opportunistic sampling. In other words, the system and methods may check for timer expiration on a periodic basis. In other aspects, the system and methods may not utilize opportunistic sampling.

In one or more exemplary aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer program product such as a machine readable medium, i.e., a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to carry or store desired program code in the form of instructions or data structures and that may be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

Although selected aspects have been illustrated and described in detail, it will be understood that various substitutions and alterations may be made therein without departing from the spirit and scope of the present invention, as defined by the following claims. 

1. A method of controlling power at a central processing unit, the method comprising: moving to a higher CPU frequency after a transient performance deadline has expired; entering an idle state; and resetting the transient performance deadline based on an effective transient budget.
 2. The method of claim 1, further comprising: exiting the idle state.
 3. The method of claim 2, further comprising: determining whether a CPU frequency has increased to meet a transient deadline.
 4. The method of claim 3, further comprising: rescheduling a timer when the CPU has not increased in order to meet a transient deadline.
 5. The method of claim 1, further comprising: determining an upcoming CPU frequency for an upcoming busy cycle.
 6. The method of claim 5, wherein the effective transient budget is determined by multiplying the transient response deadline by a next higher CPU frequency and dividing a result by a difference between the next higher CPU frequency step and the upcoming frequency, wherein the next higher CPU frequency is one step higher than the upcoming frequency.
 7. The method of claim 6, further comprising: adding an overhead to the effective transient budget.
 8. The method of claim 7, wherein the overhead comprises a clock switch overhead, a clock scheduling overhead, a voltage change overhead, or a combination thereof.
 9. The method of claim 8, further comprising: setting a deadline to jump to a higher CPU frequency equal to an end idle time plus the effective transient budget and the overhead.
 10. The method of claim 8, further comprising: setting a deadline to jump to a higher CPU frequency equal to a current time plus the effective transient budget and the overhead.
 11. A device, comprising: means for moving to a higher CPU frequency after a transient performance deadline has expired; means for entering an idle state; and means for resetting the transient performance deadline based on an effective transient budget.
 12. The device of claim 11, further comprising: means for exiting the idle state.
 13. The device of claim 12, further comprising: means for determining whether a CPU frequency has increased to meet a transient deadline.
 14. The device of claim 13, further comprising: means for rescheduling a timer when the CPU has not increased in order to meet a transient deadline.
 15. The device of claim 11, further comprising: means for determining an upcoming CPU frequency for an upcoming busy cycle.
 16. The device of claim 15, wherein the effective transient budget is determined by multiplying the transient response deadline by a next higher CPU frequency and dividing a result by a difference between the next higher CPU frequency step and the upcoming frequency, wherein the next higher CPU frequency is one step higher than the upcoming frequency.
 17. The device of claim 16, further comprising: means for adding an overhead to the effective transient budget.
 18. The device of claim 17, wherein the overhead comprises a clock switch overhead, a clock scheduling overhead, a voltage change overhead, or a combination thereof.
 19. The device of claim 18, further comprising: means for setting a deadline to jump to a higher CPU frequency equal to an end idle time plus the effective transient budget and the overhead.
 20. The device of claim 18, further comprising: means for setting a deadline to jump to a higher CPU frequency equal to a current time plus the effective transient budget and the overhead.
 21. A device, comprising: a processor, wherein the processor is operable to: move to a higher CPU frequency after a transient performance deadline has expired; enter an idle state; and reset the transient performance deadline based on an effective transient budget.
 22. The device of claim 21, wherein the processor is further operable to: exit the idle state.
 23. The device of claim 22, wherein the processor is further operable to: determine whether a CPU frequency has increased to meet a transient deadline.
 24. The device of claim 23, wherein the processor is further operable to: reschedule a timer when the CPU has not increased in order to meet a transient deadline.
 25. The device of claim 21, wherein the processor is further operable to: determine an upcoming CPU frequency for an upcoming busy cycle.
 26. The device of claim 25, wherein the effective transient budget is determined by multiplying the transient response deadline by a next higher CPU frequency and dividing a result by a difference between the next higher CPU frequency step and the upcoming frequency, wherein the next higher CPU frequency is one step higher than the upcoming frequency.
 27. The device of claim 26, wherein the processor is further operable to: add an overhead to the effective transient budget.
 28. The device of claim 27, wherein the overhead comprises a clock switch overhead, a clock scheduling overhead, a voltage change overhead, or a combination thereof.
 29. The device of claim 28, wherein the processor is further operable to: set a deadline to jump to a higher CPU frequency equal to an end idle time plus the effective transient budget and the overhead.
 30. The device of claim 28, wherein the processor is further operable to: set a deadline to jump to a higher CPU frequency equal to a current time plus the effective transient budget and the overhead.
 31. A memory medium, comprising: at least one instruction for moving to a higher CPU frequency after a transient performance deadline has expired; at least one instruction for entering an idle state; and at least one instruction for resetting the transient performance deadline based on an effective transient budget.
 32. The memory medium of claim 31, further comprising: at least one instruction for exiting the idle state.
 33. The memory medium of claim 32, further comprising: at least one instruction for determining whether a CPU frequency has increased to meet a transient deadline.
 34. The memory medium of claim 33, further comprising: at least one instruction for rescheduling a timer when the CPU has not increased in order to meet a transient deadline.
 35. The computer program product of claim 31, further comprising: at least one instruction for determining an upcoming CPU frequency for an upcoming busy cycle.
 36. The memory medium of claim 35, wherein the effective transient budget is determined by multiplying the transient response deadline by a next higher CPU frequency and dividing a result by a difference between the next higher CPU frequency step and the upcoming frequency, wherein the next higher CPU frequency is one step higher than the upcoming frequency.
 37. The memory medium of claim 36, further comprising: at least one instruction for adding an overhead to the effective transient budget.
 38. The memory medium of claim 37, wherein the overhead comprises a clock switch overhead, a clock scheduling overhead, a voltage change overhead, or a combination thereof.
 39. The memory medium of claim 38, further comprising: at least one instruction for setting a deadline to jump to a higher CPU frequency equal to an end idle time plus the effective transient budget and the overhead.
 40. The memory medium of claim 38, further comprising: at least one instruction for setting a deadline to jump to a higher CPU frequency equal to a current time plus the effective transient budget and the overhead. 